S1D13706F00A200 Epson, S1D13706F00A200 Datasheet - Page 25

• Manufacturer Part Number: S1D13706F00A200
• Description: LCD Drivers (QVGA) 320x240 LCD Controller @ 8bpp
• Manufacturer: Epson

Specifications of S1D13706F00A200

• Maximum Clock Frequency: 33 MHz
• Operating Supply Voltage: 1.8 V to 2.2 V, 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-100
• Attached Touch Screen: No
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Epson Research and Development
Vancouver Design Center
4.4 Summary of Configuration Options
Hardware Functional Specification
Issue Date: 2008/12/16
CNF4,CNF[2:0]
Configuration
S1D13706
CNF[7:6]
CNF3
CNF5
Input
Select host bus interface as follows:
Note: The host bus interface is 16-bit only.
Configure GPIO pins as inputs at power-on
WAIT# is active high
CLKI to BCLK divide select:
These pins are used for configuration of the S1D13706 and must be connected directly to
NIOV
state at any other time has no effect.
CNF4
CNF7
1 (connected to NIOV
1
0
1
0
1
0
1
0
1
0
1
0
1
0
X
0
0
1
1
DD
Table 4-7: Summary of Power-On/Reset Options
or V
CNF2
CNF6
SS
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
1
0
1
. The state of CNF[6:0] is latched on the rising edge of RESET#. Changing
CNF1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
DD
)
Revision 10.3
CNF0
Power-On/Reset State
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
CLKI to BCLK Divide Ratio
1 : 1
2 : 1
3 : 1
4 : 1
Host Bus
SH-4/SH-3 interface, Big Endian
SH-4/SH-3 interface, Little Endian
MC68K #1, Big Endian
Reserved
MC68K #2, Big Endian
Reserved
Generic #1, Big Endian
Generic #1, Little Endian
Reserved
Generic #2, Little Endian
REDCAP2, Big Endian
Reserved
DragonBall (MC68EZ328/MC68VZ328), Big Endian
Reserved
Reserved
Configure GPIO pins as outputs at power-on (for use
by HR-TFT/D-TFD when selected)
WAIT# is active low
0 (Connected to V
SS
)
X31B-A-001-10
S1D13706
Page 25