R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 88

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 6 Instruction Descriptions
(2) Structure Access Instructions
These instructions reference memory by specifying a 12-bit displacement located in the instruction
code. An MOVU unsigned load instruction that automatically performs execution of zero
extension has also been added.
(3) Bit Manipulation Instructions (Operating on Memory)
The BAND.B, BOR.B, and BXOR.B instructions perform logical operations between a bit in
memory and the T bit, and store the result in the T bit. The BCLR.B and BSET.B instructions
manipulate a bit in memory. The BST.B and BLD.B instructions execute a transfer between a bit
in memory and the T bit. The BANDNOT.B and BORNOT.B instructions perform logical
operations between the value resulting from inverting a bit in memory and the T bit, and store the
result in the T bit. The BLDNOT.B instruction inverts a bit in memory and stores the result in the
T bit. Bits other than the specified bit are not affected.
(4) Bit Manipulation Instructions (Operating on a General Register)
The BCLR and BSET instructions manipulate one of the LSB 8 bits of a general register Rn. The
BST and BLD instructions execute a transfer between one of the LSB 8 bits of a general register
Rn and the T bit. Bits other than the specified bit are not affected.
Rev. 3.00 Jul 08, 2005 page 72 of 484
REJ09B0051-0300
MOV.B/W/L Rm, @(disp12, Rn), MOV.B/W/L @(disp12, Rm), Rn
MOVU.B/W @(disp12, Rm), Rn
FMOV.S FRm, @(disp12, Rn), FMOV.S @(disp12, Rm), FRn
FMOV.D DRm, @(disp12, Rn), FMOV.D @(disp12, Rm), DRn
BAND.B #imm3, @(disp12, Rn), BOR.B #imm3, @(disp12, Rn)
BCLR.B #imm3, @(disp12, Rn), BSET.B #imm3, @(disp12, Rn)
BST.B #imm3, @(disp12, Rn), BLD.B #imm3, @(disp12, Rn)
BXOR.B #imm3, @(disp12, Rn)
BANDNOT.B #imm3, @(disp12, Rn), BORNOT.B #imm3, @(disp12, Rn)
BLDNOT.B #imm3, @(disp12, Rn)
BCLR #imm3, Rn, BSET #imm3, Rn
BST #imm3, Rn , BLD #imm3, Rn