R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 43

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

3.7
3.7.1
There are five kinds of instruction that can initiate exception handling: the TRAP instruction, slot
illegal instructions, general illegal instructions, integer division instructions, and floating-point
operation instructions. These are summarized in table 3.8.
Table 3.8
Type
Trap instruction
Slot illegal
instruction
General illegal
instruction
Integer division
exception
Floating-point
operation
instruction
Instruction Exceptions
Types of Instruction Exception
Instruction Exception Types
Source Instruction
TRAPA
Undefined code (FPU instruction or
FPU-related CPU instruction in module
standby status including FPU or in
product with no FPU, or register bank-
related instruction in product with no
register bank) located immediately after
delayed branch instruction (in delay
slot), instruction that modifies PC, 32-
bit instruction, RESBANK instruction,
DIVS instruction, or DIVU instruction
Undefined code (FPU instruction, FPU-
related CPU instruction, or register
bank-related instruction in module
standby status including FPU or in
product with no FPU) not in delay slot
Division by zero
Negative maximum value ÷ (-1)
Instruction causing invalid operation
defined by IEEE754 standard or
division-by-zero exception, instruction
causing overflow, underflow, or inexact
exception
Rev. 3.00 Jul 08, 2005 page 27 of 484
Notes
Delayed branch instructions: JMP,
JSR, BRA, BSR, RTS, RTE, BF/S,
BT/S, BSRF, BRAF
Register bank-related instructions:
RESBANK, LDBANK, STBANK
Instructions that modify PC: JMP,
JSR, BRA, BSR, RTS, RTE, BT, BF,
TRAPA, BF/S, BT/S, BSRF, BRAF,
JSR/N, RTV/N
32-bit instructions: BAND.B,
BANDNOT.B, BCLR.B, BLD.B,
BLDNOT.B, BOR.B, BORNOT.B,
BSET.B, BST.B, BXOR.B, FMOV.S
@disp12, FMOV.D @disp12,
MOV.B @disp12, MOV.W @disp12,
MOV.L @disp12, MOVI20,
MOVI20S, MOVU.B, MOVU.W
DIVU, DIVS
DIVS
FADD, FSUB, FMUL, FDIV, FMAC,
FCMP/EQ, FCMP/GT, FLOAT,
FTRC, FCNVDS, FCNVSD, FSQRT
Section 3 Exception Handling
REJ09B0051-0300