R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 217

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

6.4.25
Format
JSR
Description
Branches to the subroutine procedure at the address specified by register indirect addressing. The
PC value is stored in the PR. The jump destination is an address specified by the 32-bit data in
general register Rm. The stored/saved PC is the address four bytes after this instruction. The JSR
instruction and RTS instruction are used together for subroutine procedure calls.
Note
Since this is a delayed branch instruction, the instruction after JSR is executed before branching.
No interrupts and address errors are accepted between this instruction and the next instruction. If
the next instruction is a branch instruction, it is acknowledged as an illegal slot instruction.
Operation
JSR(long m)
{
}
PR=PC;
PC=R[m]+4;
Delay_Slot(PR+2);
@Rm
JSR
Branch to Subroutine Procedure
/* JSR @Rm */
PC → PR, Rm → PC
Abstract
Jump to SubRoutine
Code
0100mmmm00001011
Rev. 3.00 Jul 08, 2005 page 201 of 484
Section 6 Instruction Descriptions
Branch Instruction
Delayed Branch Instruction
Cycle
2
REJ09B0051-0300
T Bit
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