R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 46

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 3 Exception Handling
An FPU exception is generated only when the corresponding enable bit is set. When the FPU
detects an exception, FPU operation is halted and exception generation is reported to the CPU.
When exception handling is started, CPU operations are as follows.
1. The start address of the exception service routine stored in VBR + H'00000034 is fetched from
2. SR contents are saved on the stack.
3. PC is saved on the stack. The PC value saved is the start address of the instruction following
4. Control branches to the address stored in VBR + H'00000034.
The exception flag bits in FPSCR are always updated regardless of whether or not an FPU
exception has been accepted, and remain set until explicitly cleared by the user by means of an
instruction. The FPSCR source bits change each time an FPU instruction is executed.
When the V bit in the enable field of the FPSCR register is set and the QIS bit in FPSCR is also
set, FPU exception handling is started when qNaN or ±∞ is input to a floating-point operation
instruction source.
3.8
There are cases, as shown in table 3.9, in which, if an address error, RAM error, FPU exception,
register bank error (overflow), or interrupt occurs immediately after a delayed branch instruction,
the exception is not accepted immediately, but is held pending. In such cases, the exception will
be accepted when an instruction for which exception acceptance is permitted is decoded.
Table 3.9
Notes:
Rev. 3.00 Jul 08, 2005 page 30 of 484
REJ09B0051-0300
Point of Occurrence
Immediately after a
delayed branch
instruction*
the exception handling vector table.
the last instruction executed.
×
*
FADD, FSUB, FMUL, FDIV, FMAC, FCMP/EQ, FCMP/GT, FLOAT, FTRC,
FCNVDS, FCNVSD, FSQRT
: Not accepted
Cases in Which Exceptions Are Not Accepted
Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,
BRAF
Exception Source Occurrence Immediately after Delayed Branch Instruction
Address
Error
×
RAM Error
×
FPU
Exception
×
Exception Source
Register Bank
Error (Overflow)
×
Interrupt
×