R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 106

IC SUPERH MPU ROMLESS 240QFP

R5S72030W200FP

Manufacturer Part Number
R5S72030W200FP
Description
IC SUPERH MPU ROMLESS 240QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Datasheets

Specifications of R5S72030W200FP

Core Processor
SH2A-FPU
Core Size
32-Bit
Speed
200MHz
Connectivity
CAN, I²C, SCI, SSI, SSU, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
82
Program Memory Type
ROMless
Ram Size
80K x 8
Voltage - Supply (vcc/vdd)
1.1 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
240-QFP
For Use With
R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-

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Section 6 Instruction Descriptions
6.3.2
Format
BANDNOT.B #imm3,
@(disp12,Rn)
Description
ANDs the value obtained by inverting a specified bit of memory at the address indicated by (disp
+ Rn) with the T bit, and stores the result in the T bit. The bit number is specified by 3-bit
immediate data. With this instruction, data is read from memory as a byte unit.
Operation
Rev. 3.00 Jul 08, 2005 page 90 of 484
REJ09B0051-0300
BANDNOTM (long d, long i, long n)
}
BANDNOT.B #imm3, @(disp12, Rn)
{
long disp, imm, temp, assignbit;
disp = (0x00000FFF & (long)d);
imm= (0x00000007&(long)i);
temp= (long) Read_Byte (R[n]+disp);
assignbit =(0x00000001<<imm)&temp;
if((T==1)&&(assignbit==0)) T=1;
else T=0;
PC+=4;
BANDNOT
Bit NOT Logical AND
Abstract
~ (<imm> of (disp+Rn)) & T
→ T
Bit ANDNOT
Code
0011nnnn0iii10011100dddddddddddd 3
/*BANDNOT.B #imm3, @(disp12, Rn) */
Bit Manipulation Instruction
SH-2A/SH2A-FPU (New)
Cycle T Bit
Operation
result

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