R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 36

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 3 Exception Handling
Table 3.4
Note: VBR: Vector base register
3.2
3.2.1
A reset is the highest-priority exception handling source. There are two types of reset: a power-on
reset and a manual reset. The CPU state is initialized by both a power-on reset and a manual reset.
The FPU state is initialized by a power-on reset, but not by a manual reset. Refer to the hardware
manual of the relevant product for information on the states of on-chip peripheral modules, the
PFC, and I/O ports.
3.2.2
When a power-on reset condition is detected, the chip enters the power-on reset state. See
“Power-On Reset” in the Exception Handling section of the hardware manual for the relevant
product for details of power-on reset conditions.
When the power-on reset state is released, power-on reset exception handling is started. CPU
operations are as follows.
1. The initial value of the program counter (PC) (i.e. the execution start address) is fetched from
2. The initial value of the stack pointer (SP) is fetched from the exception vector table.
3. The vector base register (VBR) is cleared to H'00000000, the interrupt mask bits (I3 to I0) in
Rev. 3.00 Jul 08, 2005 page 20 of 484
REJ09B0051-0300
Exception Source
Reset
Address error, RAM error,
register bank error, interrupt,
instruction
the exception vector table.
the status register (SR) are set to (H'F) (1111), and the BO and CS bits are initialized to 0. The
BN bit in IBNR of INTC is also initialized to 0. In addition, in products with an FPU, FPSCR
is initialized to H'00040001.
Vector table address offset: See table 3.3.
Vector number: See table 3.3.
Resets
Types of Reset
Power-On Reset
Exception Vector Table Address Calculation
Vector Table Address Calculation
Vector table address = (vector table address offset)
Vector table address = VBR + (vector table address offset)
= (vector number) × 4
= VBR + (vector number) × 4