R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 296

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 6 Instruction Descriptions
6.5.3
Description
1. When FPSCR.PR = 0: Arithmetically compares the two single-precision floating-point
2. When FPSCR.PR = 1: Arithmetically compares the two double-precision floating-point
3. When FPSCR.PR = 0: Arithmetically compares the two single-precision floating-point
4. When FPSCR.PR = 1: Arithmetically compares the two double-precision floating-point
Operation
Rev. 3.00 Jul 08, 2005 page 280 of 484
REJ09B0051-0300
No. PR Format
1.
2.
3.
4.
void FCMP_EQ(int m,n) /* FCMP/EQ
{
}
void FCMP_GT(int m,n) /* FCMP/GT
{
numbers in FRn and FRm, and stores 1 in the T bit if they are equal, or 0 otherwise.
numbers in DRn and DRm, and stores 1 in the T bit if they are equal, or 0 otherwise.
numbers in FRn and FRm, and stores 1 in the T bit if FRn > FRm, or 0 otherwise.
numbers in DRn and DRm, and stores 1 in the T bit if DRn > DRm, or 0 otherwise.
0
1
0
1
pc += 2;
clear_cause();
if(fcmp_chk (m,n) == INVALID) fcmp_invalid();
else if(fcmp_chk (m,n) == EQ)
else
pc += 2;
clear_cause();
if ((fcmp_chk (m,n) == INVALID) ||
FCMP
Floating-Point
Comparison
FCMP/EQ FRm,FRn (FRn==FRm)?1:0 → T
FCMP/EQ DRm,DRn (DRn==DRm)?1:0 → T
FCMP/GT FRm,FRn (FRn>FRm)?1:0 → T
FCMP/GT DRm,DRn (DRn>DRm)?1:0 → T
(fcmp_chk (m,n) == UO)) fcmp_invalid();
Floating-point CoMPare
Abstract
FRm,FRn */
FRm,FRn */
T = 1;
T = 0;
Code
1111nnnnmmmm0100 1
1111nnn0mmm00100 2
1111nnnnmmmm0101 1
1111nnn0mmm00101 2
Floating-Point Instruction
Cycle
T Bit
1/0
1/0
1/0
1/0