R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 413

IC SUPERH MPU ROMLESS 240QFP

R5S72030W200FP

Manufacturer Part Number
R5S72030W200FP
Description
IC SUPERH MPU ROMLESS 240QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Datasheets

Specifications of R5S72030W200FP

Core Processor
SH2A-FPU
Core Size
32-Bit
Speed
200MHz
Connectivity
CAN, I²C, SCI, SSI, SSU, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
82
Program Memory Type
ROMless
Ram Size
80K x 8
Voltage - Supply (vcc/vdd)
1.1 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
240-QFP
For Use With
R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-

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(b) When a MULS.W instruction is immediately followed by a MULS.W, MULU.W, DMULS.L,
(c) When a MULS.W instruction is immediately followed by an LDS.L (memory) instruction
Instruction Issuance
These instructions use the multiplier.
These instructions lock the multiplier for a 1-slot interval.
Parallel Execution Capability
No particular comments
MULS.W Rm,Rn
STS
Instruction after next
MULS.W Rm,Rn
LDS.L
Instruction after next
DMULU.L, MUL.L, MULR, STS (register). STS.L (memory), or LDS (register) instruction
As the MULS.W instruction locks the multiplier, parallel execution is not possible.
Parallel execution with the MULS.W instruction is not possible, as it locks the multiplier.
MACL,Rn
@Rn+,MACL
↔ ↔ ↔ ↔ ↔ ↔ Slots
↔ ↔ ↔ ↔ ↔ ↔ Slots
IF
IF
IF
IF
ID
ID
IF
IF
mm
mm
ID
ID
ID
ID
mm
mm
EX
EX
EX
EX
WB
MA
⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅
⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅
Rev. 3.00 Jul 08, 2005 page 397 of 484
WB
Section 8 Pipeline Operation
REJ09B0051-0300

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