R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 33

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

3.1.2
Table 3.2 shows the timing of detection and the start of exception handling for each exception
source.
Table 3.2
Exception Handling
Reset
Address error
RAM error
Interrupt
Register
bank error
Instruction
Exception Handling Operation
Timing of Exception Source Detection and Start of Exception Handling
Power-on reset
Manual reset
Bank underflow
Bank overflow
Trap instruction
General illegal
instruction
Slot illegal
instruction
Integer division
instruction
Floating-point
operation
instruction
Exception Source Detection and Start of Exception Handling
Started by detection of power-on reset condition
Started by detection of manual reset condition
Detected when instruction is decoded; exception handling is
started after completion of currently executing instruction
Started upon attempted execution of RESBANK instruction when
save has not been performed to register bank
Started when save has already been performed to all register
bank areas when acceptance of register overflow exception has
been set by interrupt controller, and interrupt that uses register
bank is generated and accepted by CPU
Started by execution of TRAPA instruction
Started when undefined code (FPU instruction or FPU-related
CPU instruction in module standby status including FPU or in
product with no FPU, or register bank-related instruction in
product with no register bank) not immediately following delayed
branch instruction (delay slot) is decoded
Started when undefined code (FPU instruction or FPU-related
CPU instruction in module standby status including FPU or in
product with no FPU, or register bank-related instruction in
product with no register bank) not immediately following delayed
branch instruction (delay slot), instruction that modifies PC, 32-bit
instruction, RESBANK instruction, DIVS instruction, or DIVU
instruction is decoded
Started upon detection of division-by-zero exception or overflow
exception caused by dividing negative maximum value
(H’80000000) by –1
Started by floating-point operation instruction invalid operation
exception (stipulated by IEEE754), or overflow, underflow, or
imprecision interrupt. Also started when qNaN or ±∞ is input to a
floating-point operation instruction source
Rev. 3.00 Jul 08, 2005 page 17 of 484
Section 3 Exception Handling
REJ09B0051-0300