R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 285

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

6.4.65
Format
TRAPA #imm
Description
Starts the trap exception processing. The PC and SR values are stored on the stack, and the
program branches to an address specified by the vector. The vector is a memory address obtained
by zero-extending the 8-bit immediate data and then quadrupling it. The PC is the start address of
the next instruction. TRAPA and RTE are both used together for system calls.
Note
For the Renesas Technology Super H RISC engine assembler, declarations should use scaled
values (×4) as displacement values.
Operation
TRAPA(long i) /* TRAPA #imm */
{
}
long imm;
imm=(0x000000FF & i);
R[15]-=4;
Write_Long(R[15],SR);
R[15]-=4;
Write_Long(R[15],PC–2);
PC=Read_Long(VBR+(imm<<2))+4;
TRAPA
Trap Exception
Handling
Abstract
PC/SR → Stack area, (imm × 4 + VBR)
→ PC
TRAP Always
Rev. 3.00 Jul 08, 2005 page 269 of 484
Code
11000011iiiiiiii 5
Section 6 Instruction Descriptions
System Control Instruction
REJ09B0051-0300
Cycle
T Bit
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