R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 362

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 8 Pipeline Operation
(2) When the succeeding instruction writes to the destination register or flag of the preceding
Rev. 3.00 Jul 08, 2005 page 346 of 484
REJ09B0051-0300
ADD R3,R4
MOV R5,R4
MOV.L @R0,R1
MOV.L @R2,R1
CLIPS.B R3
CLIPS.B R4
MOV
MULR
MOV
MOVMU.L@R15+,R13
Figure 8.20 Example of Contention Due to Instruction that Overwrites Destination of
Figure 8.21 Example of Contention Due to Instruction that Overwrites Destination of
instruction. (However, contention only occurs if an instruction other than a multiply
instruction, divide instruction, LDBANK instruction, RESBANK instruction, MOVMU
instruction, or MOVML instruction writes to registers and flags other than the FPU register
and CS bit. No contention is detected with a multiply instruction, divide instruction, LDBANK
instruction, or RESBANK instruction. In addition, contention is only detected for Rn with the
MOVMU instruction and for R0 with the MOVML instruction. No contention occurs if either
of these instructions write to other registers.) (Figures 8.20 to 8.25)
R5,R6
R0,R6
R5,R6
Figure 8.22 Example of No Contention in Case of CS Bit
Figure 8.24 Example of MOVMU.L No Contention
Figure 8.23 Example of MULR No Contention
IF
IF
IF
IF
ID
—
ID
—
IF
IF
IF
IF
IF
IF
Preceding Instruction 1
Preceding Instruction 2
EX
ID
EX
—
ID
ID
ID
ID
ID
ID
EX
MA
ID
EX
EX
EX
mm
EX
EX
EX
mm
MA
mm
MA
WB
MA
WB