R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 34

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 3 Exception Handling
When exception handling is initiated, the CPU operates as follows.
(1) Reset Exception Handling
The initial values of the program counter (PC) and stack pointer (SP) are fetched from the
exception vector table (addresses H'00000000 and H'00000004 in the case of a power-on reset,
and addresses H'00000008 and H'0000000C in the case of a manual reset). See section 3.1.3,
Exception Vector Table, for details of the exception vector table. Next, the vector base register is
cleared to H'00000000, the interrupt mask bits (I3 to I0) in the status register (SR) are set to (H'F)
(1111), and the BO and CS bits are initialized to 0. The BN bit in IBNR of INTC is also
initialized to 0. In addition, in products with an FPU, FPSCR is initialized to H'00040001.
Program execution starts from the PC address fetched from the exception vector table.
(2) Address Error, RAM Error, Register Bank Error, Interrupt, or Instruction Exception
Handling
SR and PC are saved on the stack indicated by R15. In interrupt exception handling other than
NMI and UBC, when register bank use has been set, general registers R0 to R14, control register
GBR, system registers MACH, MACL, and PR, and the vector table address offset of the interrupt
exception handling to be executed, are saved to the register bank. In the case of exception
handling due to an address error, RAM error, register bank error, NMI interrupt or UBC interrupt,
saving to a register bank is not performed. Also, when saving is performed to all register banks,
automatic saving to the stack is performed instead of register bank saving. In this case, an
interrupt controller setting must have been made for register bank overflow exceptions not to be
accepted. If a setting has been made for register bank overflow exceptions to be accepted, a
register bank overflow exception will be generated. In the case of interrupt exception handling,
the interrupt priority level is written to the interrupt mask bits (I3 to I0) in SR. In address error,
RAM error, and instruction exception handling, bits I3 to I0 are not affected. Next, the start
address is fetched from the exception vector table and program execution is started from that
address.
3.1.3
Exception Vector Table
Before exception handling is executed, the exception vector table must have been set up in
memory. The exception vector table holds the start addresses of the exception service routines
(the reset exception handling table holds the initial values of PC and SP).
A different vector number and vector table address offset are assigned to each exception source.
The vector table address is calculated from the corresponding vector number and vector table
address offset. In exception handling, the start address of the exception service routine is fetched
from the exception vector table entry indicated by this vector table address.
Rev. 3.00 Jul 08, 2005 page 18 of 484
REJ09B0051-0300