R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 327

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

6.5.15
Description
When FPSCR.PR = 0, this instruction inverts the SZ bit in floating-point register FPSCR.
Changing the SZ bit in FPSCR switches FMOV instruction data transfer between one single-
precision data unit and a data pair. When FPSCR.SZ = 0, the FMOV instruction transfers one
single-precision data unit. When FPSCR.SZ = 1, the FMOV instruction transfers two single-
precision data units as a pair.
If FPSCR.PR = 1, the instruction is handled as an illegal instruction.
Operation
Possible Exceptions:
None
PR
0
1
void FSCHG()
{
}
Format
FSCHG
—
if(FPSCR_PR == 0){
}
else undefined_operation();
FSCHG
SZ Bit
Inversion
FPSCR ^= 0x00100000; /* bit 20 */
PC += 2;
/* FSCHG */
Abstract
FPSCR.SZ=~FPSCR.SZ
—
Sz-bit CHanGe
Code
1111001111111101 1
—
Rev. 3.00 Jul 08, 2005 page 311 of 484
Section 6 Instruction Descriptions
Floating-Point Instruction
Cycle
—
REJ09B0051-0300
T Bit
—
—