R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 15

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10 Simple Method of Calculating Required Number of Clock Cycles.................................. 475
Appendix A SH-2A/SH2A-FPU Parallel Execution
Appendix B Programming Guidelines (Using MOVI20 and MOVI20S)
Slots and Pipeline Flow .................................................................................................... 339
Instruction Execution and Parallel Execution Capability ................................................. 341
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
8.3.7
Number of Instruction Execution States ........................................................................... 351
Effect of Memory Load Instruction on Pipeline ............................................................... 352
Contention Due to FPU..................................................................................................... 353
Contention Due to Multiplier............................................................................................ 360
Programming Strategy ...................................................................................................... 364
Pipeline Operations for Each Instruction .......................................................................... 364
8.9.1
8.9.2
8.9.3
8.9.4
8.9.5
8.9.6
8.9.7
8.9.8
Details of Resource Contention ........................................................................... 342
Details of Contention Due to Wait for Result of Previously Issued Instruction .. 345
Details of Register Contention and Flag Contention ........................................... 345
Details of Contention Due to Multi-Cycle Instruction......................................... 347
Details of Contention Due to 32-Bit Instruction.................................................. 348
Details of Contention Due to Instruction that Uses FPSCR ................................ 349
Details of Contention Due to Branch Instruction................................................. 350
Data Transfer Instructions ................................................................................... 378
Arithmetic Operation Instructions ....................................................................... 390
Logical Operation Instructions ............................................................................ 404
Shift Instructions.................................................................................................. 412
Branch Instructions.............................................................................................. 414
System Control Instructions................................................................................. 422
Exception Handling ............................................................................................. 443
Floating-Point Instructions and FPU-Related CPU Instructions.......................... 448
Rev. 3.00 Jul 08, 2005 page xiii of xiv
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