R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 358

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 8 Pipeline Operation
8.3.1
As there is only one each of pipelines other than integer pipelines, if a preceding instruction and
succeeding instruction attempt to use such a pipeline simultaneously, contention occurs and the
succeeding instruction has to wait to be executed. Cases in which contention occurs are as
follows.
(1) When the preceding instruction and succeeding instruction are both instructions accompanying
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REJ09B0051-0300
Previously issued instruction
Previously issued instruction
Preceding instruction
Succeeding instruction
Note: Box indicates reference slot.
MOV.L @R1+,R2
MOV.L @R1+,R3
Note: There is a maximum of one memory access (MA) per slot.
LDS
MOV.L R1,@R3
Note: Contention between LDS instruction and memory write instruction
a memory access (figure 8.8)
Alternatively, in the case of a combination of a CPU → FPU data transfer instruction and
memory write instruction (figure 8.8), or a combination with another FPU → CPU data
transfer instruction.
In these cases, memory access pipeline contention occurs.
Figure 8.7 Definitions of Preceding, Succeeding, and Previously Issued Instructions
R0,FPUL
Details of Resource Contention
Figure 8.9 Example of Contention between LDS Instrunction
Figure 8.8 Example of Memory Access Contention
IF
IF
IF
IF
IF
and Memory Write Instruction
ID
DF
—
IF
IF
ID
—
ID
ID
IF
IF
EX
ID
EX
EX
ID
EX
EX
ID
ID
MA
EX
NA
EX
MA
MA
EX
E1
MA
SF
WB
E2
SF
: CPU pipeline
: FPU pipeline
: CPU pipeline