R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 248

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 6 Instruction Descriptions
6.4.37
Format
MULS.W Rm,Rn
MULS
Description
Performs 16-bit multiplication of the contents of general registers Rn and Rm, and stores the 32-
bit result in the MACL register. The operation is signed and the MACH register data does not
change.
Operation
Example:
Rev. 3.00 Jul 08, 2005 page 232 of 484
REJ09B0051-0300
MULS(long m,long n) /* MULS Rm,Rn */
{
}
MULS R0,R1
STS
MACL=((long)(short)R[n]*(long)(short)R[m]);
PC+=2;
MACL,R0 ; Operation result
Rm,Rn
MULS.W
Signed
Multiplication
; Before execution:
; After execution:
Abstract
Signed operation, Rn × Rm → MACL
MULtiply as Signed Word
R0 = H'FFFFFFFE, R1 = H'00005555
MACL = H'FFFF5556
Code
0010nnnnmmmm1111
Arithmetic Instruction
Cycle
1
T Bit
—