R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 380
R5S72030W200FP
Manufacturer Part Number
R5S72030W200FP
Description
IC SUPERH MPU ROMLESS 240QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Specifications of R5S72030W200FP
Core Processor
SH2A-FPU
Core Size
32-Bit
Speed
200MHz
Connectivity
CAN, I²C, SCI, SSI, SSU, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
82
Program Memory Type
ROMless
Ram Size
80K x 8
Voltage - Supply (vcc/vdd)
1.1 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
240-QFP
For Use With
R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
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Section 8 Pipeline Operation
8.8
The following programming points should be noted in order to improve instruction execution
speed.
(1) A branch destination address should be at a longword boundary in memory. This enables
(2) The first 3 instructions immediately after an instruction that performs a load from memory
(3) The first 3 instructions immediately after a 32-bit multiply instruction should not include an
(4) Instructions immediately following a floating-point arithmetic operation instruction, and
8.9
Pipeline operations for each instruction are described below. In conjunction with the previously
described rules and possibility of parallel execution, this information allows the program pipeline
flow and number of instruction execution states to be calculated.
“Instruction A” in the following pipeline diagrams denotes the instruction being described.
The “Instruction Issuance” description indicates in particular how the instruction should be treated
when taking resource contention into consideration.
The “Parallel Execution Capability” description indicates in particular how the instruction should
be treated when taking parallel execution capability into consideration. Cases are described here
in which there is no register contention.
The number of stages and number of execution states of an instruction are indicated using the
format below. These tables show the number of states when the instruction is executed without
register dependency.
Rev. 3.00 Jul 08, 2005 page 364 of 484
REJ09B0051-0300
parallel execution to be performed efficiently immediately after a branch.
should not include an instruction that uses the same register as the load instruction destination
register. If possible, an instruction that uses the destination register should be no earlier than
the fourth instruction after the load instruction.
instruction that uses the same register as the result register.
having a latency between 1 and twice the latency of the floating-point arithmetic operation
instruction, should not use the destination register of the floating-point arithmetic operation
instruction.
Programming Strategy
Pipeline Operations for Each Instruction
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