R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 387

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Branch
instructions
System
control
instructions
Type
Conditional
branch
instructions
Delayed
conditional
branch
instructions
Unconditio
nal branch
instructions
Unconditio
nal branch
instructions
with no
delay
System
control
ALU
instructions
Category
of Stages
Number
3
3
3
3
5
3
5
3
4
3
Execution
States
3/1 *
2/1 *
2
3
5
1
3
1
2
1
1
1
Latency
3/1 *
2/1 *
2
3
5
1
2
1
0
2
1
1
1
• These instruc-
• These instruc-
• These instruc-
• These instruc-
• This instruction
• This instruction
tions use the
branch pipeline.
tions use the
branch pipeline.
tions use the
branch pipeline.
tions use the
branch pipeline.
uses the branch
pipeline.
uses the
memory access
pipeline.
Contention
Rev. 3.00 Jul 08, 2005 page 371 of 484
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—
Section 8 Pipeline Operation
BF
BT
BS/F
BT/S
BRA
BRAF
BSR
BSRF
JMP
JSR
RTS
JSR/N
RTS/N
RTV/N
JSR/N
CLRT
LDC
LDC
LDC
LDC
LDS
NOP
SETT
STC
STC
STC
STC
STS
Instructions
REJ09B0051-0300
label
label
label
label
label
Rm
label
Rm
@Rm
@Rm
@Rm
Rm
@@(disp,TBR)
Rm,SR
Rm,GBR
Rm,TBR
Rm,VBR
Rm,PR
SR,Rn
GBR,Rn
TBR,Rn
VBR,Rn
PR,Rn