R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 312
R5S72030W200FP
Manufacturer Part Number
R5S72030W200FP
Description
IC SUPERH MPU ROMLESS 240QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Specifications of R5S72030W200FP
Core Processor
SH2A-FPU
Core Size
32-Bit
Speed
200MHz
Connectivity
CAN, I²C, SCI, SSI, SSU, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
82
Program Memory Type
ROMless
Ram Size
80K x 8
Voltage - Supply (vcc/vdd)
1.1 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
240-QFP
For Use With
R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
R5S72030W200FP
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SAMSUNG
Quantity:
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Part Number:
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Manufacturer:
Renesas Electronics America
Quantity:
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Section 6 Instruction Descriptions
6.5.10
Description
When FPSCR.PR = 0: Taking the contents of FPUL as a 32-bit integer, converts this integer to a
single-precision floating-point number and stores the result in FRn.
When FPSCR.PR = 1: Taking the contents of FPUL as a 32-bit integer, converts this integer to a
double-precision floating-point number and stores the result in DRn.
When FPSCR.enable.I = 1, and FPSCR.PR = 0, an FPU exception trap is generated regardless of
whether or not an exception has occurred. When an exception occurs, correct exception
information is reflected in FPSCR.cause and FPSCR.flag, and FRn or DRn is not updated.
Appropriate processing should therefore be performed by software.
Rev. 3.00 Jul 08, 2005 page 296 of 484
REJ09B0051-0300
PR
0
1
Format
FLOAT FPUL,FRn
FLOAT FPUL,DRn
FLOAT
Integer to Floating-Point
Conversion
Abstract
(float)FPUL → FRn
(double)FPUL → DRn
Floating-point
convert from integer
Code
1111nnnn00101101 1
1111nnn000101101 2
Floating-Point Instruction
Cycle
T Bit
—
—
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