R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 374

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 8 Pipeline Operation
When a register (FR0 to FR15, or FPUL) that stores the result of a floating-point arithmetic
operation instruction is written to (used as a destination register) by a following floating-point
arithmetic operation instruction or floating-point load/store instruction, the next instruction is kept
waiting before being executed. The number of cycles by which execution is delayed is [latency –
1] cycles if the preceding operation was FDIV or FSQRT, and [latency – 2] cycles otherwise
(figures 8.48 and 8.49).
Rev. 3.00 Jul 08, 2005 page 358 of 484
REJ09B0051-0300
Floating-point arithmetic
operation instruction
(double-precision)
(FADD DR0,DR2)
(remains at latency 8)
Next floating-point
load/store instruction
(single-precision)
(FMOV FR2,FR4)
Floating-point arithmetic
operation instruction
(single-precision)
(FDIV FR1,FR2)
(latency 12 → latency 11)
Next floating-point
load/store instruction
(single-precision)
(FMOV FR3,FR2)
Figure 8.47 Example of No Latency Reduction with Double-Precision Arithmetic
Figure 8.48 Example of Contention Due to Overwriting (FDIV, FSQRT)
IF
⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ED E1 E2 SF
DF E1 E1 E1 E1 E1 E1 E2 SF
—
Operation Instruction
IF
—
—
DF EX NA SF
—
—
—
—
—
DF EX NA SF