R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 453

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

(12) RTE Instruction
Instruction Type
Pipeline
Operation
The pipeline ends after eight stages: IF, ID, EX, MA, MA, EX, EX, EX. RTE is a delayed branch
instruction. The ID stage of the delay slot instruction is stalled for a 5-slot interval. The IF stage
of the branch destination instruction is started from the slot after the second MA stage of RTE.
Instruction Issuance
This instruction does not cause resource contention.
Parallel Execution Capability
This is a multi-cycle instruction, and cannot be executed in parallel with a subsequent instruction.
Instruction A
Delay slot
Branch destination
RTE
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ Slots
IF
IF
ID
—
EX
—
MA
—
MA
—
EX
—
IF
Rev. 3.00 Jul 08, 2005 page 437 of 484
EX
ID
—
Section 8 Pipeline Operation
EX
EX
ID
⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅
EX
REJ09B0051-0300
⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅