R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 498

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Appendix A SH-2A/SH2A-FPU Parallel Execution
MR,MU
EX
MU
• The first and last steps of multi-step instructions are executed in parallel.
• FPU instructions follow the SH4 classifications ((1) LS type, (2) FE type, (3) CO type). The new 32-bit FMOV
• As a rule, 32-bit instructions are executed in parallel if the preceding instruction is a multi-step instruction.
• The MOVMU.L and MOVML.L instructions cannot be executed in parallel with the instructions that follow
• Parallel execution of delayed branch instructions and delayed slots is not supported.
Multi-step instructions:
32-bit instructions:
32-bit FMOV instructions:
Memory-Tbit bit-manipulation instructions:
Delayed branch instructions:
Rev. 3.00 Jul 08, 2005 page 482 of 484
REJ09B0051-0300
Instruction
cation of
Classifi-
instructions belong to the (1) LS type.
They cannot be executed in parallel with the instructions that follow them. However, pairs of memory-Tbit bit-
manipulation instructions are executed in parallel.
them.
TRAPA, MOVMU.L, MOVML.L, AND.B, OR.B, TST.B, XOR.B, TAS.B, BCLR.B, BSET.B, BST.B, BAND.B,
BANDNOT.B, BLD.B, BLDNOT.B, BOR.B, BORNOT.B, BXOR.B, MUL.L, DMULS.L, DMULU.L, MULR,
DIVU, DIVS, FCMP/EQ DRm,DRn, FCMP/GT DRm,DRn, LDC Rm,SR, STC SR,Rn, LDC.L @Rm+,SR,
STC.L SR,@-Rn, LDBANK, STBANK, RESBANK, FMOV.D, FMOV DRm,DRn, JSR/N @@(disp,TBR),
SLEEP, RTE, MAC.W, MAC.L
MOVI20, MOVI20S, MOV.B @(disp12,Rm),Rn, MOV.W @(disp12,Rm),Rn, MOV.L @(disp12,Rm),Rn,
MOV.B Rm,@(disp12,Rn), MOV.W Rm,@(disp12,Rn), MOV.L Rm,@(disp12,Rn),MOVU.B, MOVU.W,
FMOV.S @(disp12,Rm),FRn, FMOV.D @(disp12,Rm),DRn, FMOV.S FRm,@(disp12,Rn), FMOV.D
DRm,@(disp12,Rn), BCLR.B, BSET.B, BST.B, BAND.B, BANDNOT.B, BLD.B, BLDNOT.B, BOR.B,
BORNOT.B, BXOR.B
FMOV.S @(disp12,Rm),FRn, FMOV.D @(disp12,Rm),DRn, FMOV.S FRm,@(disp12,Rn), FMOV.D
DRm,@(disp12,Rn),
BAND.B, BANDNOT.B, BLD.B, BLDNOT.B, BOR.B, BORNOT.B, BXOR.B
BRA, BSR, BRAF, BSRF, JMP, JSR, RTS, RTE, BT/S, BF/S
First
MR
MR
MR
Instruction
cation of
Classifi-
Second
RESBANK(BO==1)
BAND.B
BLDNOT.B
BXOR.B
SLEEP
MAC.W
#imm3,@(disp12,Rn) BANDNOT.B #imm3,@(disp12,Rn) BLD.B
#imm3,@(disp12,Rn) BOR.B
#imm3,@(disp12,Rn) LDC.L
@Rm+,@Rn+
TST.B
MAC.L
Instruction
#imm3,@(disp12,Rn) BORNOT.B #imm3,@(disp12,Rn)
@Rm+,SR
#imm,@(R0,GBR)
@Rm+,@Rn+
RTE
#imm3,@(disp12,Rn)