R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 49

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

4.1
All instructions are RISC type. Their features are detailed in this section.
(1) 16-Bit Fixed-Length Instructions
Basic instructions have a fixed length of 16 bits, increasing program code efficiency.
(2) Addition of 32-Bit Fixed-Length Instructions
The SH-2A/SH2A-FPU features the addition of 32-bit fixed-length instructions, improving
performance and ease of use.
(3) One Instruction/Cycle
Basic instructions can be executed in one cycle using the pipeline system.
(4) Data Length
Longword is the standard data length for all operations. Memory can be accessed in bytes, words,
or longwords. Byte or word data accessed from memory is sign-extended and calculated with
longword data. Immediate data is sign-extended for arithmetic operations or zero-extended for
logic operations. It also is calculated with longword data.
Table 4.1
SH-2A/SH2A-FPU CPU
MOV.W
ADD
.DATA.W
Note: The address of the immediate data is accessed by @(disp, PC).
(5) Load-Store Architecture
Basic operations are executed between registers. For operations that involve memory access, data
is loaded to the registers and executed (load-store architecture). Instructions such as AND that
manipulate bits, however, are executed directly in memory.
.........
RISC-Type Instruction Set
@(disp,PC),R1
R1,R0
H'1234
Sign Extension of Word Data
Section 4 Instruction Features
Description
Data is sign-extended to 32
bits, and R1 becomes
H'00001234. It is next
operated upon by an ADD
instruction.
Rev. 3.00 Jul 08, 2005 page 33 of 484
Example for Other CPU
ADD.W
Section 4 Instruction Features
#H'1234,R0
REJ09B0051-0300