R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 47
R5S72030W200FP
Manufacturer Part Number
R5S72030W200FP
Description
IC SUPERH MPU ROMLESS 240QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Specifications of R5S72030W200FP
Core Processor
SH2A-FPU
Core Size
32-Bit
Speed
200MHz
Connectivity
CAN, I²C, SCI, SSI, SSU, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
82
Program Memory Type
ROMless
Ram Size
80K x 8
Voltage - Supply (vcc/vdd)
1.1 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
240-QFP
For Use With
R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5S72030W200FP
Manufacturer:
SAMSUNG
Quantity:
1 001
Company:
Part Number:
R5S72030W200FP
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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3.9
Table 3.10 shows the stack status after completion of exception handling.
Table 3.10 Stack Status after Exception Handling
Address
error
RAM error
Register
bank error
(underflow)
Trap
instruction
General
illegal
instruction
Type
Stack Status after Exception Handling
SP
SP
SP
SP
SP
Address of instruction
following executed
instruction
SR
Address of instruction
following executed
instruction
SR
Start address of
relevant RESBANK
instruction
SR
Address of instruction
following TRAPA
instruction
SR
Start address of
general illegal
instruction
SR
Stack Status
(32 bits)
(32 bits)
(32 bits)
(32 bits)
(32 bits)
(32 bits)
(32 bits)
(32 bits)
(32 bits)
(32 bits)
Interrupt
Register
bank error
(overflow)
Integer
division
instruction
(division
by zero,
overflow)
Slot illegal
instruction
FPU
exception
Type
Rev. 3.00 Jul 08, 2005 page 31 of 484
SP
SP
SP
SP
SP
Address of instruction
following executed
instruction
SR
Address of instruction
following executed
instruction
SR
Start address of
relevant integer
division instruction
SR
Jump destination
address of delayed
branch instruction
SR
Address of instruction
following executed
instruction
SR
Section 3 Exception Handling
Stack Status
REJ09B0051-0300
(32 bits)
(32 bits)
(32 bits)
(32 bits)
(32 bits)
(32 bits)
(32 bits)
(32 bits)
(32 bits)
(32 bits)
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