R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 344

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 7 Register Banks
7.3
7.3.1
Figure 7.2 illustrates the register bank save operations. The following operations are performed
when an interrupt for which register bank use is allowed by IBCR is received by the CPU.
Figure 7.3 illustrates the register bank save timing. Saving to the bank takes place between the
start of interrupt exception processing and the start of the fetch of the first instruction in the
exception service routine.
Rev. 3.00 Jul 08, 2005 page 328 of 484
REJ09B0051-0300
(a) Assume that the IBNR bank number value, BN, is i before the interrupt is generated.
(b) The contents of registers R0 to R14, GBR, MACH, MACL, PR, and the interrupt vector
(c) The BN value is incremented by 1.
table address offset (VTO) are saved to the bank indicated by the BN, bank i.
(c)
Bank Save and Retrieve Operations
Save to Bank
BN
+1
Figure 7.2 Bank Save Operations
(a)
Register banks
Bank N-1
Bank i+1
Bank 0
Bank 1
Bank i
(b)
R0 to R14
Registers
MACH
MACL
GBR
VTO
PR