R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 349

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 7 Register Banks
7.6
SR Register Bank Overflow Bit (BO Bit)
The BO bit is modified when the contents of the SR register are retrieved by the RTE instruction.
The BO bit is not modified when a RESBANK instruction is executed. The BO bit is set to 1 if
exception generation by the interrupt controller is not enabled in cases where a bank overflow
occurs during an interrupt. If exception generation by the interrupt controller is enabled for cases
when a bank overflow occurs during an interrupt, the BO bit is not modified. The BO bit is
modified by the LDC Rm.SR and LDC.L @Rmt.SR instructions.
Rev. 3.00 Jul 08, 2005 page 333 of 484
REJ09B0051-0300