R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 369

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

8.6
When a register (FR0 to FR15, or FPUL) that stores the result of a floating-point arithmetic
operation instruction, FMOV instruction, or floating-point load instruction is read (used as a
source register) by a following floating-point arithmetic operation instruction or FMOV FRm,FRn
instruction, the next instruction is issued after completion of the operation. As a result, that
instruction is kept waiting for a period equivalent to the latency cycle of the preceding operation
instruction (figure 8.35). A zero-latency instruction can be executed in parallel with the
succeeding instruction even if the succeeding instruction uses the result register as its source
(figure 8.36).
When a register (FR0 to FR15) that stores the result of a floating-point arithmetic operation
instruction is read (used as a source register) by a following FMOV or STS.L instruction, and the
value is output to memory, latency is shortened by 1 cycle (figure 8.37).
Figure 8.37 Example of Writing Result to Memory Immediately Following FPU Operation
Floating-point arithmetic operation
instruction (single-precision)
(FADD FR1,FR2) (latency 3)
Next floating-point instruction
(single-precision)
(FMOV FR2,FR3)
Floating-point instruction
(single-precision)
(FMOV FR0,FR2) (latency 0)
Next floating-point arithmetic operation
instruction (single-precision)
(FADD FR2,FR3)
Floating-point arithmetic operation
instruction (single-precision)
(FADD FR0,FR2)
Next floating-point instruction
(single-precision)
(FMOV FR2,@R3)
Figure 8.35 Example of Use of FPU Operation Result by Succeeding Instruction
Figure 8.36 Example of Use of Result of Zero-Latency Instruction as Source
Contention Due to FPU
IF
IF
IF
IF
DF
IF
DF
DF
DF
IF
E1
—
EX
E1
E1
—
Rev. 3.00 Jul 08, 2005 page 353 of 484
E2
—
NA
E2
E2
DF
SF
DF
SF
SF
SF
EX
Section 8 Pipeline Operation
EX
NA
REJ09B0051-0300
NA
SF