R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 460
R5S72030W200FP
Manufacturer Part Number
R5S72030W200FP
Description
IC SUPERH MPU ROMLESS 240QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Specifications of R5S72030W200FP
Core Processor
SH2A-FPU
Core Size
32-Bit
Speed
200MHz
Connectivity
CAN, I²C, SCI, SSI, SSU, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
82
Program Memory Type
ROMless
Ram Size
80K x 8
Voltage - Supply (vcc/vdd)
1.1 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
240-QFP
For Use With
R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5S72030W200FP
Manufacturer:
SAMSUNG
Quantity:
1 001
Company:
Part Number:
R5S72030W200FP
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 8 Pipeline Operation
When there is banking and no overflow, saving to the bank is performed automatically. The
pipeline ends after eight stages: IF, ID, EX, EX, MA, MA, MA, EX.
When there is banking and overflow, registers saved to the bank are automatically restored, and
the BO bit is set to 1. The pipeline ends after 27 stages: IF, ID, EX, EX, MA, MA, MA, EX, MA,
MA, MA, MA, MA, MA, MA, MA, MA, MA, MA, MA, MA, MA, MA, MA, MA, MA, MA.
After the first two stages there are two repetitions of EX, three repetitions of MA, one EX, and 19
repetitions of MA.
Interrupt exception handling is not a delayed branch. The IF stage of the branch destination
instruction is started from the slot containing the third MA stage of the interrupt exception
handling.
Interrupt sources comprise external interrupt request pins such as NMI, a user break, and interrupts
by on-chip peripheral modules.
Interrupt Acceptance
Interrupt exception handling is not accepted in a delay slot.
If a multi-cycle instruction is currently being executed, interrupt exception handling is not
accepted until after execution of that instruction is completed. However, a DIVU or DIVS
instruction can be canceled during execution, allowing the interrupt to be accepted.
Rev. 3.00 Jul 08, 2005 page 444 of 484
REJ09B0051-0300
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