R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 388
R5S72030W200FP
Manufacturer Part Number
R5S72030W200FP
Description
IC SUPERH MPU ROMLESS 240QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Specifications of R5S72030W200FP
Core Processor
SH2A-FPU
Core Size
32-Bit
Speed
200MHz
Connectivity
CAN, I²C, SCI, SSI, SSU, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
82
Program Memory Type
ROMless
Ram Size
80K x 8
Voltage - Supply (vcc/vdd)
1.1 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
240-QFP
For Use With
R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5S72030W200FP
Manufacturer:
SAMSUNG
Quantity:
1 001
Company:
Part Number:
R5S72030W200FP
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 8 Pipeline Operation
System
control
instructions
Rev. 3.00 Jul 08, 2005 page 372 of 484
REJ09B0051-0300
Type
LDC.L
instructions
STC.L
instructions
LDS.L
instruction
(PR)
STS.L
instruction
(PR)
Register
→ MAC
transfer
instructions
Memory
→ MAC
transfer
instructions
MAC →
register
transfer
instructions
MAC →
memory
transfer
instructions
RTE
instruction
RESBANK
instruction
LDBANK
instruction
STBANK
instruction
Category
of Stages
Number
11/23 *
7
5
5
4
5
4
4
5
4
4
8
8
9
2
Execution
States
9/19 *
5
1
2
1
1
1
1
1
1
1
6
6
7
2
Latency
8/20 *
4
2
2
1
2
1
1
2
2
1
5
5
6
2
• These instruc-
• These instruc-
• This instruction
• These instruc-
• These instruc-
• These instruc-
• These instruc-
• When the BO
tions use the
memory access
pipeline.
tions use the
memory access
pipeline.
uses the
memory access
pipeline.
tions lock the
multiplier for 1
state.
tions lock the
multiplier for 2
states.
tions use the
multiplication
result read path.
tions use the
multiplication
result read path.
bit is 1, this
instruction uses
the memory
access pipeline.
Contention
—
—
—
LDC.L
LDC.L
LDC.L
STC.L
STC.L
STC.L
LDS.L
STS.L
CLRMAC
LDS
LDS
LDS.L
LDS.L
STS
STS
STS.L
STS.L
RTE
RESBANK
LDBANK @Rm,R0
STBANK R0,@Rn
Instructions
@Rm+,SR
@Rm+,GBR
@Rm+,VBR
SR,@-Rn
GBR,@-Rn
VBR,@-Rn
@Rm+,PR
PR,@-Rn
Rm,MACH
Rm,MACL
@Rm+,MACH
@Rm+,MACL
MACH,Rn
MACL,Rn
MACH,@-Rn
MACL,@-Rn
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