R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 175

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

6.4.3
Format
ADDV Rm,Rn
Description
Adds general register Rn data to Rm data, and stores the result in Rn. If an overflow occurs, the T
bit is set to 1.
Operation
ADDV(long m,long n)
{
}
long dest,src,ans;
if ((long)R[n]>=0) dest=0;
else dest=1;
if ((long)R[m]>=0) src=0;
else src=1;
src+=dest;
R[n]+=R[m];
if ((long)R[n]>=0) ans=0;
else ans=1;
ans+=dest;
if (src==0 || src==2) {
}
else T=0;
PC+=2;
ADDV
Binary Addition
with Overflow Check
if (ans==1) T=1;
else T=0;
Abstract
Rn + Rm → Rn, overflow → T
ADD with (V flag) overflow check
/*ADDV Rm,Rn */
Code
0011nnnnmmmm1111
Rev. 3.00 Jul 08, 2005 page 159 of 484
Section 6 Instruction Descriptions
Arithmetic Instruction
Cycle
1
REJ09B0051-0300
T Bit
Overflow