R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 41

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

3.6
3.6.1
Interrupt exception handling can be initiated by an NMI, a user break, the H-UDI, an external
interrupt, or an on-chip peripheral module, as shown in table 3.6.
Table 3.6
Each interrupt source is assigned a different vector number and vector table offset. For details of
vector numbers and vector table address offsets, see “Interrupt Exception Vectors and Priority” in
the Interrupt Controller section of the hardware manual for the relevant product.
Note: For details and numbers of external interrupts (IRQ) and on-chip peripheral module
3.6.2
Interrupt sources are assigned priority levels. If a number of interrupts occur simultaneously
(multiple interruption), the priority order is determined by the interrupt controller (INTC) and
exception handling is initiated accordingly.
Interrupt source priority levels are expressed as values from 0 to 16, with 0 representing the lowest
priority level and 16 the highest. The NMI interrupt is the highest-priority interrupt at level 16; it
cannot be masked and is always accepted. The user break interrupt and H-UDI are assigned
priority level 15. The priority level of IRQ interrupts and on-chip peripheral module interrupts can
be set as desired in the interrupt priority level setting registers of the INTC (see table 3.7). Priority
levels 0 to 15, but not 16, can be set. For details of the interrupt priority level setting registers, see
the Interrupt Controller section of the hardware manual for the relevant product.
Type
NMI
User break
H-UDI
External interrupt (IRQ),
on-chip peripheral module
request sources, see “Interrupt Sources” in the Interrupt Controller section of the hardware
manual for the relevant product.
Interrupts
Interrupt Sources
Interrupt Priority
Interrupt Sources
Request Source
NMI pin (external input)
User break controller
User debug interface
External interrupt pin, on-chip peripheral
module
Rev. 3.00 Jul 08, 2005 page 25 of 484
Section 3 Exception Handling
Number of Sources
1
1
1
See Note
REJ09B0051-0300