R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 19

IC SUPERH MPU ROMLESS 240QFP

R5S72030W200FP

Manufacturer Part Number
R5S72030W200FP
Description
IC SUPERH MPU ROMLESS 240QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Datasheets

Specifications of R5S72030W200FP

Core Processor
SH2A-FPU
Core Size
32-Bit
Speed
200MHz
Connectivity
CAN, I²C, SCI, SSI, SSU, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
82
Program Memory Type
ROMless
Ram Size
80K x 8
Voltage - Supply (vcc/vdd)
1.1 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
240-QFP
For Use With
R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-

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2.1
Data formats supported by the SH-2A/SH2A-FPU are shown in figure 2.1.
2.2
2.2.1
Figure 2.2 shows the general registers. There are 16 general registers (Rn) numbered R0 to R15,
which are 32 bits in length. General registers are used for data processing and address calculation.
R0 is also used as an index register. Several instructions use R0 as a fixed source or destination
register. R15 is used as the hardware stack pointer (SP). Saving and recovering the status register
(SR) and program counter (PC) in exception processing is accomplished by referencing the stack
using R15.
Byte (8 bits)
Word (16 bits)
Longword (32 bits)
Single-precision floating-point (32 bits)
Double-precision floating-point (64 bits)
Data Formats
Register Configuration
General Registers
Section 2 Programming Model
Figure 2.1 Data Formats
63 62
s
exp
51
Rev. 3.00 Jul 08, 2005 page 3 of 484
Section 2 Programming Model
31
31 30
s
fraction
exp
22
REJ09B0051-0300
15
fraction
7
0
0
0
0
0

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