R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 32

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 3 Exception Handling
Table 3.1
Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,
Rev. 3.00 Jul 08, 2005 page 16 of 484
REJ09B0051-0300
Reset
Address errors
RAM errors
Instructions
Register bank
errors
Interrupts
Instructions
2. Register bank-related instructions: RESBANK, LDBANK, STBANK
3. Instructions that modify PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA, BF/S,
4. 32-bit instructions: BAND.B, BANDNOT.B, BCLR.B, BLD.B, BLDNOT.B, BOR.B,
BRAF
BT/S, BSRF, BRAF, JSR/N, RTV/N
BORNOT.B, BSET.B, BST.B, BXOR.B, FMOV.S @disp12, FMOV.D @disp12,
MOV.B @disp12, MOV.W @disp12, MOV.L @disp12, MOVI20, MOVI20S, MOVU.B,
MOVU.W
Exception Types and Priority
Exception Handling
Power-on reset
Manual reset
CPU address error
DMAC address error
RAM error
FPU exception
Integer division exception (division by zero)
Integer division exception (overflow)
Bank underflow
Bank overflow
NMI
User break
H-UDI
External interrupt (IRQ)
On-chip peripheral modules
Trap instruction (TRAPA instruction)
General illegal instruction (undefined code)
Slot illegal instruction (undefined code (FPU instruction or FPU-
related CPU instruction in module standby status including FPU or in
product with no FPU, or register bank-related instruction *
with no register bank) located immediately after delayed branch
instruction *
RESBANK instruction, DIVS instruction, or DIVU instruction)
1
, instruction that modifies PC *
3
, 32-bit instruction *
2
in product
4
,
Priority
High
Low