R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 305

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

6.5.6
Description
When FPSCR.PR = 0: Arithmetically divides the single-precision floating-point number in FRn by
the single-precision floating-point number in FRm, and stores the result in FRn.
When FPSCR.PR = 1: Arithmetically divides the double-precision floating-point number in DRn
by the double-precision floating-point number in DRm, and stores the result in DRn.
When FPSCR.enable.O/U/I is set, an FPU exception trap is generated regardless of whether or not
an exception has occurred. When an exception occurs, correct exception information is reflected in
FPSCR.cause and FPSCR.flag, and FRn or DRn is not updated. Appropriate processing should
therefore be performed by software.
Operation
PR
0
1
void FDIV(int m,n)
{
Format
FDIV FRm,FRn
FDIV DRm,DRn
pc += 2;
clear_cause();
if((data_type_of(m) == sNaN) ||
else if((data_type_of(m) == qNaN) ||
else switch (data_type_of(m)){
FDIV
Floating-Point
Division
(data_type_of(n) == sNaN)) invalid(n);
case NORM: switch (data_type_of(n)){
(data_type_of(n) == qNaN)) qnan(n);
case PINF:
case NINF:
case PZERO:
case NZERO:
default:
Abstract
FRn/FRm → FRn
DRn/DRm → DRn
Floating-point DIVide
/* FDIV FRm,FRn */
normal_fdiv(m,n);
inf(n,sign_of(m)^sign_of(n));break;
zero(n,sign_of(m)^sign_of(n));break;
Code
1111nnnnmmmm0011 10
1111nnn0mmm00011 23
Rev. 3.00 Jul 08, 2005 page 289 of 484
break;
Section 6 Instruction Descriptions
Floating-Point Instruction
Cycle
REJ09B0051-0300
T Bit
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