R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 75

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

CLIPS.W Rn
CLIPU.B Rn
CLIPU.W Rn
DIV1
DIV0S
DIV0U
DIVS
DIVU
DMULS.L Rm, Rn
DMULU.L Rm, Rn
DT
EXTS.B
EXTS.W Rm, Rn
EXTU.B
EXTU.W Rm, Rn
MAC.L
@Rn+
MAC.W
@Rn+
MUL.L
Instruction
Rm, Rn
Rm, Rn
R0, Rn
R0, Rn
Rn
Rm, Rn
Rm, Rn
@Rm+,
@Rm+,
Rm, Rn
0100nnnn10010101 When Rn > (H'00007FFF),
0100nnnn10000001 When Rn > (H'000000FF),
0100nnnn10000101 When Rn > (H'0000FFFF),
0011nnnnmmmm0100 1-step division (Rn ÷ Rm)
0010nnnnmmmm0111 MSB of Rn → Q, MSB of Rm → M,
0000000000011001 0→M/Q/T
0100nnnn10010100 Signed, Rn ÷ R0 → Rn
0100nnnn10000100 Unsigned, Rn ÷ R0 → Rn
0011nnnnmmmm1101 Signed, Rn × Rm → MACH, MACL
0011nnnnmmmm0101 Unsigned, Rn × Rm → MACH,
0100nnnn00010000 Rn - 1 → Rn; when Rn = 0, 1 → T
0110nnnnmmmm1110 Rm sign-extended from byte → Rn
0110nnnnmmmm1111 Rm sign-extended from word → Rn
0110nnnnmmmm1100 Rm zero-extended from byte → Rn
0110nnnnmmmm1101 Rm zero-extended from word → Rn
0000nnnnmmmm1111 Signed, (Rn) × (Rm) + MAC
0100nnnnmmmm1111 Signed, (Rn) × (Rm) + MAC
0000nnnnmmmm0111 Rn × Rm → MACL
Code
(H'00007FFF) → Rn, 1 → CS
When Rn < (H'FFFF8000),
(H'FFFF8000) → Rn, 1 → CS
(H'000000FF) → Rn, 1 → CS
(H'0000FFFF) → Rn, 1 → CS
M ^ Q → T
32 ÷ 32 → 32 bits
32 ÷ 32 → 32 bits
32 × 32 → 64 bits
MACL
32 × 32 → 64 bits
When Rn ≠ 0, 0 → T
→ MAC
32 × 32 + 64 → 64 bits
→ MAC
16 × 16 + 64 → 64 bits
32 × 32 → 32 bits
Operation
Rev. 3.00 Jul 08, 2005 page 59 of 484
Cycles
36
34
1
1
1
1
1
1
2
2
1
1
1
1
1
4
3
2
Calculati-
on result
Calculati-
on result
Com-
parison
result
Section 5 Instruction Set
T Bit
―
―
―
―
―
―
―
―
―
―
―
―
―
―
0
REJ09B0051-0300
SH2E SH4
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Compatibility
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
SH-2A/
SH2A-
New
FPU
Yes
Yes
Yes
Yes
Yes