R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 6

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Item
4.3 Instruction
Format
Table 4.8
Instruction Formats
5.1 Instruction Set
by Classification
Table 5.2
Instruction Code
Format
5.1.1 Data Transfer
Instructions
Table 5.3 Data
Transfer Instructions
6.2 Format of
Instruction
Descriptions
6.3.30 RESBANK
REStore from
registerBANK
System Control
Instruction
6.4.21 DT
Decrement and Test
Arithmetic Instruction
6.4.31 MOV
MOVe immediate
data
Data Transfer
Instruction
Rev. 3.00 Jul 08, 2005 page iv of xiv
Page
45
53
56
76
145
196
219
Revision (See Manual for Details)
Table amended
Table amended
Table amended
MOVML.L @R15+,Rn
MOVMU.L @R15+,Rn
Note: When Rn = R15, read Rn as PR
Description amended
Register bank structure definition
(VTO: Interrupt vector table address offset)
Note amended
* 19 when a bank overflow has occurred and the register is
restored from the stack
Program listing amended
DT R5
Description amended
⋅⋅⋅ The PC points to the starting address of the fourth byte after this
MOV instruction. ⋅⋅⋅ The PC points to the starting address of the
fourth byte after this MOV instruction,⋅⋅⋅
Instruction Formats
nid format
32
15
Item
Instruction
xxxx
xxxx
dddd
nnnn
Format
dddd
x i i i
dddd
xxxx
Explanation
Rm:
Rn:
imm:
disp:
16
0
Source register
Destination register
Immediate data
Displacement *
1