UPD70F3763GC-UEU-AX Renesas Electronics America, UPD70F3763GC-UEU-AX Datasheet - Page 95
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
UPD70F3763GC-UEU-AX
Manufacturer Part Number
UPD70F3763GC-UEU-AX
Description
MCU 32BIT V850ES/JX3-U 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3763GC-UEU-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
75
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3763GC-UEU-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 95 of 1411
- Download datasheet (8Mb)
V850ES/JG3-U, V850ES/JH3-U
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
16-bit timer/event counter AA (TAA)
(n = 0 to 5, m = 0 to 3, 5)
16-bit timer/event counter AB (TAB)
(n = 0, 1)
Motor control
TMT
Watchdog timer 2 (WDT2)
Real-time output function (RTO)
A/D converter
I
CRC
2
C00 to I
Number of clocks necessary for access = 3 + i + j + (2 + j) × k
Caution Accessing the above registers is prohibited in the following statuses.
Remark
Peripheral Function
2
C02
generated, it can only be cleared by a reset.
• When the CPU operates with the subclock and the main clock oscillation is stopped
• When the CPU operates with the internal oscillation clock
i: Values (0) of higher 4 bits of VSWC register
j: Values (0 or 1) of lower 4 bits of VSWC register
TAAnCNT
TAAnCCR0, TAAnCCR1
TAAmIOC4
TABnCNT
TABnCCR0 to TABnCCR3
TABnIOC4
TAB0OPT1
TAB0DTC
TT0CNT
TT0TCR0, TT0TCR1
WDTM2
RTBL0, RTBH0
ADA0M0
ADA0CR0 to ADA0CR11
ADA0CR0H to ADA0CR11H
IICS0 to IICS2
CRCD
Register Name
Read
Write
Read
Write
Read
Read
Write
Read
Write
Read
Write
Write
Read
Write
Read
Write
(when WDT2 operating)
Write
(RTPC0.RTPOE0 bit = 0)
Read
Read
Read
Read
Write
Access
CHAPTER 3 CPU FUNCTION
1 or 2
• 1st access: No wait
• Continuous write: 0 to 3
1 or 2
• 1st access: No wait
• Continuous write: 0 to 3
1 or 2
1 or 2
• 1st access: No wait
• Continuous write: 0 to 3
1 or 2
• 1st access: No wait
• Continuous write: 0 to 3
1 or 2
• 1st access: No wait
• Continuous write: 0 to 3
• 1st access: No wait
• Continuous write: 0 to 3
1 or 2
• 1st access: No wait
• Continuous write: 0 to 3
1 or 2
3
1
1 or 2
1 or 2
1 or 2
1
1
If a wait cycle is
k
Page 95 of 1408
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