UPD70F3763GC-UEU-AX Renesas Electronics America, UPD70F3763GC-UEU-AX Datasheet - Page 419
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
UPD70F3763GC-UEU-AX
Manufacturer Part Number
UPD70F3763GC-UEU-AX
Description
MCU 32BIT V850ES/JX3-U 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3763GC-UEU-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
75
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3763GC-UEU-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 419 of 1411
- Download datasheet (8Mb)
V850ES/JG3-U, V850ES/JH3-U
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
Note The overflow counter is set arbitrarily by software in the internal RAM.
<1> Read the TABnCCRm register (setting of the default value of the TIABnm pin input).
<2> An overflow occurs. Increment the overflow counter and clear the overflow flag to 0 in the overflow
<3> An overflow occurs a second time. Increment (+1) the overflow counter and clear the overflow flag to
<4> Read the TABnCCRm register.
Remark
TABnCCRm register
Overflow counter
interrupt servicing.
0 in the overflow interrupt servicing.
Read the overflow counter.
When the overflow counter is “N”, the pulse width can be calculated by (N × 10000H + D
In this example, the pulse width is (20000H + D
Clear the overflow counter (0H).
INTTABnOV signal
TIABnm pin input
16-bit counter
TABnOVF bit
m = 0 to 3,
n = 0, 1
TABnCE bit
FFFFH
0000H
Note
Example when capture trigger interval is long
0H
CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
D
m0
<1> <2>
m1
– D
1 cycle of 16-bit counter
m0
) because an overflow occurs twice.
Pulse width
D
1H
m0
<3> <4>
D
m1
2H 0H
D
m1
m1
Page 419 of 1408
– D
m0
).
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