UPD70F3763GC-UEU-AX Renesas Electronics America, UPD70F3763GC-UEU-AX Datasheet - Page 887
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UPD70F3763GC-UEU-AX
Manufacturer Part Number
UPD70F3763GC-UEU-AX
Description
MCU 32BIT V850ES/JX3-U 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3763GC-UEU-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
75
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3763GC-UEU-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 887 of 1411
- Download datasheet (8Mb)
V850ES/JG3-U, V850ES/JH3-U
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
Notes 1.
Remark
2.
WRELn
INTIICn
WRELn
INTIICn
ACKDn
MSTSn
ACKDn
MSTSn
ACKEn
ACKEn
Processing by master device
WTIMn
SDA0n
WTIMn
Transfer lines
SCL0n
n = 0 to 2
Processing by slave device
Cancel the wait during a master transmission by writing data to IICn, not by setting WRELn.
To cancel the slave wait state, write FFH to IICn or set WRELn.
SPDn
TRCn
SPDn
TRCn
STDn
SPTn
STDn
SPTn
STTn
STTn
IICn
IICn
Start condition
H
H
H
H
L
L
L
L
L
L
(When 9-Clock Wait Is Selected for Both Master and Slave) (1/3)
IICn
Figure 19-23. Example of Master to Slave Communication
AD6 AD5 AD4 AD3 AD2 AD1 AD0
1
Receive
←
Transmit
address
2
3
(a) Start condition ~ address
4
5
6
7
W
8
ACK
9
IICn
IICn
D7
←
1
←
Note 2
data Note 1
CHAPTER 19 I
FFH Note 2
D6
2
D5
3
Page 887 of 1408
D4
4
2
C BUS
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