UPD70F3763GC-UEU-AX Renesas Electronics America, UPD70F3763GC-UEU-AX Datasheet - Page 250
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UPD70F3763GC-UEU-AX
Manufacturer Part Number
UPD70F3763GC-UEU-AX
Description
MCU 32BIT V850ES/JX3-U 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3763GC-UEU-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
75
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3763GC-UEU-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 250 of 1411
- Download datasheet (8Mb)
V850ES/JG3-U, V850ES/JH3-U
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
(1) External event count mode operation flow
Remark
<1> Count operation start flow
<2> Count operation stop flow
INTTAAnCC0 signal
(TAAnCKS0 to TAAnCKS2 bits),
TAAnCCR0 register
n = 0 to 3, 5
Figure 7-17. Flow of Software Processing in External Event Count Mode
Register initial setting
16-bit counter
TAAnCTL1 register,
TAAnCCR0 register
TAAnIOC0 register,
TAAnIOC2 register,
TAAnCTL0 register
TAAnCE bit
TAAnCE bit = 1
TAAnCE bit = 0
START
FFFFH
STOP
0000H
<1>
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
D
0
Initial setting of these registers
is performed before setting the
TAAnCE bit to 1.
The TAAnCKS0 to TAAnCKS2 bits can
be set at the same time when counting
has been started (TAAnCE bit = 1).
The counter is initialized and counting
is stopped by clearing the TAAnCE bit to 0.
D
0
D
0
D
0
<2>
Page 250 of 1408
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