UPD70F3763GC-UEU-AX Renesas Electronics America, UPD70F3763GC-UEU-AX Datasheet - Page 1105

• Manufacturer Part Number: UPD70F3763GC-UEU-AX
• Description: MCU 32BIT V850ES/JX3-U 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Ur

Specifications of UPD70F3763GC-UEU-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-U, V850ES/JH3-U
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
(2) Command and Status (Offset 04H)
Bit position
31
30
29
28
27
26-25
24
23
22-21
20
19-10
9
After reset: 0210 0000H
Detected
Parity Error
Signaled
System
Error
Received
Master
Abort
Received
Target Abort
Signaled
Target Abort
Devsel
Timing[1:0]
Data Parity
Detected
Fast Back to
Back
Capable
Capabilities
Fast Back to
Back Enable
Bit name
−
−
Detected
Parity Error
Fast Back to
Back Capable
Wait Cycle
Control
Indicates the parity error status. This bit is set when an address or data parity error is
detected. This bit is cleared (0) when “1” is written via the PCI bus.
Indicates the SERR status. This bit is set when a system error occurs. This bit is cleared
(0) when “1” is written via the PCI bus.
Indicates the master’s master abort status. This bit is set when master operation is
terminated by master abort. This bit is cleared (0) when “1” is written via the PCI bus.
Indicates the master’s target abort status. This bit is set when master operation is
terminated by target abort. This bit is cleared (0) when “1” is written via the PCI bus.
Indicates the slave’s target abort status. This bit is set when slave operation is terminated
by target abort. This bit is cleared (0) when “1” is written via the PCI bus.
Indicates the DEVSEL response speed.
This field is fixed to “01” because only the Medium mode is supported.
These bits are read-only.
This bit is set when a parity error is detected during master operation. This bit is cleared (0)
when “1” is written via the PCI bus. This bit is fixed to “0” when the parity error response is
disabled with the Parity Error Response bit (Command register).
Indicates the support status of Fast Back-to-Back.
This bit is fixed to “0” because Fast Back-to-Back is not supported.
This bit is read-only.
Reserved. (Be sure to write “0” to these bits.)
Indicates that the Power Management mode is supported. This bit is fixed to “1”.
This bit is read-only.
Reserved. (Be sure to write “0” to these bits.)
Fast Back-to-Back Enable Bit
This bit is fixed to “0” because the USB host controller does not support Fast Back to Back.
This bit is read-only.
31
15
23
0
7
R/W
Signaled
System Error
Parity Error
Response
30
22
14
0
0
6
Received
Master Abort
VGA Pallet
Snoop
29
21
13
5
0
0
Capabilities
Memory Write
and Invalidate
Received
Target Abort
28
12
20
0
4
CHAPTER 21 USB HOST CONTROLLER (USBH)
Function
Signaled
Target Abort
Special
Cycle
27
19
11
0
0
3
Devsel
Timing1
Bus
Master
26
18
10
0
0
2
Fast Back to
Back Enable
Devsel
Timing0
Memory
Space
25
17
0
9
1
Data Parity
Detected
I/O Space
SERR
Enable
24
16
0
8
0
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