UPD70F3763GC-UEU-AX Renesas Electronics America, UPD70F3763GC-UEU-AX Datasheet - Page 1125
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UPD70F3763GC-UEU-AX
Manufacturer Part Number
UPD70F3763GC-UEU-AX
Description
MCU 32BIT V850ES/JX3-U 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3763GC-UEU-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
75
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3763GC-UEU-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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- Download datasheet (8Mb)
V850ES/JG3-U, V850ES/JH3-U
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
3
2
1
0
Bit position
RDE
SFE
WDHE
SOE
Bit name
Resume Detected Enable
Specifies whether to enable RD as an interrupt source.
Writing “1” to this bit sets RD as an interrupt source.
To clear this bit to “0”, write “1” to the corresponding bit of the HcInterruptDisable register.
Start Of Frame Enable
Specifies whether to enable SF as an interrupt source.
Writing “1” to this bit sets SF as an interrupt source.
To clear this bit to “0”, write “1” to the corresponding bit of the HcInterruptDisable register.
Writeback Done Head Enable
Specifies whether to enable WDH as an interrupt source.
Writing “1” to this bit sets WDH as an interrupt source.
To clear this bit to “0”, write “1” to the corresponding bit of the HcInterruptDisable register.
Scheduling Overrun Enable
Specifies whether to enable SO as an interrupt source.
Writing “1” to this bit sets SO as an interrupt source.
To clear this bit to “0”, write “1” to the corresponding bit of the HcInterruptDisable register.
1: Enables RD as an interrupt source.
0: Ignored
1: Enables SF as an interrupt source.
0: Ignored
1: Enables WDH as an interrupt source.
0: Ignored
1: Enables SO as an interrupt source.
0: Ignored
CHAPTER 21 USB HOST CONTROLLER (USBH)
Function
Page 1125 of 1408
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