UPD70F3763GC-UEU-AX Renesas Electronics America, UPD70F3763GC-UEU-AX Datasheet - Page 468
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UPD70F3763GC-UEU-AX
Manufacturer Part Number
UPD70F3763GC-UEU-AX
Description
MCU 32BIT V850ES/JX3-U 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3763GC-UEU-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
75
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3763GC-UEU-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 468 of 1411
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V850ES/JG3-U, V850ES/JH3-U
9.6.1
register if the TT0CTL0.TT0CE bit is set to 1. A square wave whose half cycle is equal to the interval can be output from
the TOT00 pin.
transferred to the CCR1 buffer register, and when the count value of the 16-bit counter matches the value of the CCR1
buffer register, a compare match interrupt request signal (INTTT0CC1) is generated. In addition, a square wave, which is
inverted when the INTTT0CC1 signal is generated, can be output from the TOT01 pin.
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
In the interval timer mode, an interrupt request signal (INTTT0CC0) is generated at the interval set by the TT0CCR0
The TT0CCR1 register is not used in the interval timer mode. However, the set value of the TT0CCR1 register is
The value of the TT0CCR0 and TT0CCR1 registers can be rewritten even while the timer is operating.
Interval timer mode (TT0MD3 to TT0MD0 bits = 0000)
INTTT0CC0 signal
TT0CCR0 register
TOT00 pin output
Count clock
selection
16-bit counter
TT0CE bit
FFFFH
0000H
TT0CE bit
Figure 9-8. Basic Timing of Operation in Interval Timer Mode
Interval (D
Figure 9-7. Configuration of Interval Timer
D
0
0
+ 1) Interval (D
CCR0 buffer register
TT0CCR0 register
16-bit counter
CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
Clear
D
0
Match signal
0
+ 1) Interval (D
D
0
D
0
0
+ 1) Interval (D
controller
Output
INTTT0CC0 signal
D
0
0
+ 1)
TOT00 pin
Page 468 of 1408
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