UPD70F3763GC-UEU-AX Renesas Electronics America, UPD70F3763GC-UEU-AX Datasheet - Page 770
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UPD70F3763GC-UEU-AX
Manufacturer Part Number
UPD70F3763GC-UEU-AX
Description
MCU 32BIT V850ES/JX3-U 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3763GC-UEU-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
75
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3763GC-UEU-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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V850ES/JG3-U, V850ES/JH3-U
18.4 Registers
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
The following registers are used to control CSIFn.
• CSIFn control register 0 (CFnCTL0)
• CSIFn control register 1 (CFnCTL1)
• CSIFn control register 2 (CFnCTL2)
• CSIFn status register (CFnSTR)
(1) CSIFn control register 0 (CFnCTL0)
CFnCTL0 is a register that controls the CSIFn serial transfer operation.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 01H.
(n = 0 to 4)
CFnCTL0
After reset: 01H
Note These bits can only be rewritten when the CFnPWR bit = 0.
Caution To forcibly suspend transmission/reception, clear the CFnPWR bit
CFnRXE
CFnPWR
CFnTXE
CFnPWR
• The CFnPWR bit controls the CSIFn operation and resets the internal circuit.
• The SOFn output is low level when the CFnTXE bit is 0.
• No reception completion interrupt is output even when the prescribed data is
transferred, and the receive data (CFnRX register) is not updated, because the
receive operation is disabled by clearing the CFnRXE bit to 0.
< >
0
1
0
1
0
1
However, CFnPWR bit = 1 can also be set at the same time as rewriting
these bits.
Note
Note
to 0 instead of the CFnRXE and CFnTXE bits.
At this time, the clock output is stopped.
R/W
CFnTXE
Disables CSIFn operation and resets the CFnSTR register
Enables CSIFn operation
Disables transmit operation
Enables transmit operation
Disables receive operation
Enables receive operation
< >
Note
Address: CF0CTL0 FFFFFD00H, CF1CTL0 FFFFFD10H,
CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
CFnRXE
Specification of transmit operation disable/enable
Specification of receive operation disable/enable
Specification of CSIFn operation disable/enable
< >
CF2CTL0 FFFFFD20H, CF3CTL0 FFFFFD30H,
CF4CTL0 FFFFFD40H
Note
CFnDIR
< >
Note
0
0
CFnTMS
Note
CFnSCE
< >
Page 770 of 1408
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