UPD70F3763GC-UEU-AX Renesas Electronics America, UPD70F3763GC-UEU-AX Datasheet - Page 501
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UPD70F3763GC-UEU-AX
Manufacturer Part Number
UPD70F3763GC-UEU-AX
Description
MCU 32BIT V850ES/JX3-U 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3763GC-UEU-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
75
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3763GC-UEU-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 501 of 1411
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V850ES/JG3-U, V850ES/JH3-U
9.6.4
to 1. When the valid edge of an external trigger input (EVTT0) is detected, 16-bit timer/event counter T starts counting,
and outputs a one-shot pulse from the TOT01 pin.
software trigger is used, the TOT00 pin outputs the active level while the 16-bit counter is counting, and the inactive level
when the counter is stopped (waiting for a trigger).
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
In the one-shot pulse output mode, 16-bit timer/event counter T waits for a trigger when the TT0CTL0.TT0CE bit is set
Instead of the external trigger input (EVTT0), a software trigger can also be generated to output the pulse. When the
external event
EVTT0 pin
trigger input/
count input)
(external
One-shot pulse output mode (TT0MD3 to TT0MD0 bits = 0011)
Note 1
Notes 1. Because the external trigger input pin (EVTT0) and external event count input pin (EVTT0) are
Internal count clock
2. Edge detector for external trigger input.
3. Edge detector for external event count input.
the same alternate-function pin, the external trigger input pin (EVTT0) cannot be used.
Set by the TT0IOC2.TT0ETS1 and TT0IOC2.TT0ETS0 bits.
Set by the TT0IOC2.TT0EES1 and TT0IOC2.TT0EES0 bits.
detector
Edge
Figure 9-25. Configuration in One-Shot Pulse Output Mode
Note 3
Software trigger
selection
generation
Count
clock
detector
Edge
TT0CE bit
Note 2
CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
control
Count
start
CCR1 buffer register
CCR0 buffer register
TT0CCR1 register
TT0CCR0 register
16-bit counter
Match signal
Match signal
Clear
Transfer
Transfer
S
R
S
R
controller
controller
(RS-FF)
(RS-FF)
Output
Output
INTTT0CC1 signal
INTTT0CC0 signal
Page 501 of 1408
TOT01 pin
TOT00 pin
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