UPD70F3763GC-UEU-AX Renesas Electronics America, UPD70F3763GC-UEU-AX Datasheet - Page 100
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UPD70F3763GC-UEU-AX
Manufacturer Part Number
UPD70F3763GC-UEU-AX
Description
MCU 32BIT V850ES/JX3-U 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3763GC-UEU-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
75
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3763GC-UEU-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 100 of 1411
- Download datasheet (8Mb)
V850ES/JG3-U, V850ES/JH3-U
Note The value written to the output latch is retained until a new value is written to the output latch.
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
Setting of PMn Register
(1) Port n register (Pn)
Data is input from or output to an external device by writing or reading the Pn register.
The Pn register consists of a port latch that holds output data, and a circuit that reads the status of pins.
Each bit of the Pn register corresponds to one pin of port n, and can be read or written in 1-bit units.
Data is written to or read from the Pn register as follows, regardless of the setting of the PMCn register.
Output mode
(PMnm = 0)
(PMnm = 1)
Input mode
Pn
After reset: 00H (output latch)
Pnm
Pn7
0
1
7
Data is written to the output latch
In the port mode (PMCn = 0), the contents of the output
latch are output from the pins.
Data is written to the output latch.
The pin status is not affected
Outputs 0.
Outputs 1.
Pn6
6
Table 4-5. Writing/Reading Pn Register
Writing to Pn Register
Pn5
5
Control of output data (in output mode)
R/W
Note
Pn4
.
7
Note
.
Pn3
3
Pn2
2
The value of the output latch is read.
The pin status is read.
CHAPTER 4 PORT FUNCTIONS
Pn1
1
Reading from Pn Register
Pn0
0
Page 100 of 1408
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