UPD70F3763GC-UEU-AX Renesas Electronics America, UPD70F3763GC-UEU-AX Datasheet - Page 524
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
UPD70F3763GC-UEU-AX
Manufacturer Part Number
UPD70F3763GC-UEU-AX
Description
MCU 32BIT V850ES/JX3-U 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3763GC-UEU-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
75
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3763GC-UEU-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 524 of 1411
- Download datasheet (8Mb)
V850ES/JG3-U, V850ES/JH3-U
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
Figure 9-37. Software Processing Flow in Free-Running Timer Mode (Compare Function) (2/2)
<1> Count operation start flow
<2> Overflow flag clear flow
<3> Count operation stop flow
(TT0CKS0 to TT0CKS2 bits)
TT0OVF bit (CLR TT0OVF).
Execute instruction to clear
Read TT0OPT0 register
Register initial setting
(check overflow flag).
TT0CCR0 register,
TT0OPT0 register,
TT0CTL1 register,
TT0IOC0 register,
TT0IOC2 register,
TT0CCR1 register
TT0CTL0 register
TT0OVF bit = 1
TT0CE bit = 1
TT0CE bit = 0
START
STOP
Yes
CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
No
Counter is initialized and
counting is stopped by
clearing TT0CE bit to 0.
Initial setting of these registers
is performed before setting the
TT0CE bit to 1.
The TT0CKS0 to TT0CKS2 bits
can be set at the same time
as when counting starts
(TT0CE bit = 1).
Page 524 of 1408
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