UPD70F3763GC-UEU-AX Renesas Electronics America, UPD70F3763GC-UEU-AX Datasheet - Page 329
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UPD70F3763GC-UEU-AX
Manufacturer Part Number
UPD70F3763GC-UEU-AX
Description
MCU 32BIT V850ES/JX3-U 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3763GC-UEU-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
75
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3763GC-UEU-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 329 of 1411
- Download datasheet (8Mb)
V850ES/JG3-U, V850ES/JH3-U
8.3
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
TIABn0
TABn includes the following hardware.
Note TAB1: EVTAB1 pin and TRGAB1 pin
Remarks 1. f
f
f
f
f
f
f
f
f
TIABn1
TIABn2
TIABn3
XX
XX
XX
XX
XX
XX
XX
XX
/2
/4
/8
/16
/32
/64
/128
Configuration
Note
Notes 1. When using the functions of the TIABn0 to TIABn3 and TOABn0 to TOABn3 pins, see Table 4-20
2. n = 0, 1
Registers
Timer inputs
Timer outputs
XX
: Main clock frequency
2. The TIAB00 pin functions alternately as a capture trigger input signal, external event count input
Using Port Pin as Alternate-Function Pin.
signal, and external trigger input signal.
Item
Note 2
Note 2
register
TABnCCR0
CCR0
buffer
TABnCNT
16-bit counter
TABn capture/compare registers 0 to 3 (TABnCCR0 to TABnCCR3)
TABn counter read buffer register (TABnCNT)
CCR0 to CCR3 buffer registers
TABn control registers 0, 1 (TABnCTL0, TABnCTL1)
TABn I/O control registers 0 to 2 (TABnIOC0 to TABnIOC2, TABnIOC4)
TABn option register 0 (TABnOPT0)
4 (TIABn0
4 (TOABn0 to TOABn3 pins)
Figure 8-1. Block Diagram of TABn
Table 8-1. Configuration of TABn
Note 1
to TIABn3 pins)
register
TABnCCR1
CCR1
buffer
CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
Internal bus
Internal bus
16-bit counter
Configuration
register
TABnCCR2
CCR2
buffer
register
TABnCCR3
buffer
CCR3
Clear
INTTABnOV
Page 329 of 1408
TOABn0
TOABn1
TOABn2
TOABn3
INTTABnCC0
INTTABnCC1
INTTABnCC2
INTTABnCC3
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