UPD70F3763GC-UEU-AX Renesas Electronics America, UPD70F3763GC-UEU-AX Datasheet - Page 616
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UPD70F3763GC-UEU-AX
Manufacturer Part Number
UPD70F3763GC-UEU-AX
Description
MCU 32BIT V850ES/JX3-U 100-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3763GC-UEU-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
75
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3763GC-UEU-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 616 of 1411
- Download datasheet (8Mb)
V850ES/JG3-U, V850ES/JH3-U
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
(2) Batch rewrite mode (transfer mode)
This mode is set by clearing the TAB1OPT0.TAB1CMS bit to 0, the TAB1OPT1.TAB1ID4 to TAB1OPT1.TAB1ID0
bits to 00000, and the TAB1OPT2.TAB1RDE bit to 0.
In this mode, the values written to each compare register are transferred to the internal buffer register all at once at
the transfer timing and compared with the counter value.
(a) Rewriting procedure
If data is written to the TAB1CCR1 register, the values set to the TAB1CCR0 to TAB1CCR3, TAB1OPT1,
TAA4CCR0, and TAA4CCR1 registers are transferred all at once to the internal buffer register at the next
transfer timing. Therefore, write to the TAB1CCR1 register last. Writing to the register is prohibited after the
TAB1CCR1 register has been written and before the transfer timing is generated (until the crest (match
between the 16-bit counter value and TAB1CCR0 register value) or the valley (match between the 16-bit
counter value and 0001H)). The operation procedure is as follows.
<1> Rewriting the TAB1CCR0, TAB1CCR2, TAB1CCR3, TAB1OPT1, TAA4CCR0, and TAA4CCR1 registers
<2> Rewriting the TAB1CCR1 register
<3> Holding the next rewriting pending until the transfer timing is generated
<4> Return to <1>.
Do not rewrite registers that do not have to be rewritten.
Rewrite the same value to the register even when it is not necessary to rewrite the TAB1CCR1 register.
Rewrite the register next time after the INTTAB1OV or INTTAB1CC0 interrupt has occurred.
CHAPTER 11 MOTOR CONTROL FUNCTION
Page 616 of 1408
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